1. Field of the Invention
The present invention relates to a method of controlling a row address strobe path and, more particularly, to a method of controlling a row address strobe path which can prevent a signal interference to a word line boosting signal at the time of enabling a word line
2. Related Prior Art
In general, in a conventional row address path as shown in FIG. 1, a RAS signal RAS1B outputted from a RAS buffer 10 is inputted to a predecoder 14 through an address controller 12, the predecoder 14 generates a plurality of row address signals AX01, AX23, AX45 and AX67 and outputs them to subsequent blocks, the row address signal AX01 among them is provided to the directly rear word line enable block 16, and the remaining row address signals AX23, AX45 and AX are provided to a row decoder (X-DEC) 20.
The RAS signal RAS1B outputted from the RAS buffer 10 is inputted into the word line enable block 16 and is used in word line enable control operation as shown in FIG. 2, the signal WL-EN outputted from the word line enable blocks 16 is applied to a word line boosting signal generator 18 so as to generate a word line boosting signal PX (refer to FIG. 2), and the word line boosting signal PX generated from the word line boosting signal generator 18 drives a word line WL decoded by the row address signal AX23, AX45 and AX67 inputted to the row decoder (refer to FIG.2).
In the conventional row address strobe path, both of the row address signal for example AX23 and the word line boosting signal PX are controlled by a RAS signal RAS1B.
In the conventional row decoder shown in FIG. 3, the word line WL is charged/discharged by the word line boosting signal PX which is controlled through a PMOS transistor P1 which is turned on/off by the row address signal AX23.
Therefore, if the row address signal AX23 falls, a first node N1 becomes logically high H, a second node N2 becomes logically low L, and a third node N3 becomes logically high H so as to turn off the PMOS transistor P1 so as to interrupt the path between the word line boosting signal PX and word line WL.
However, since the falling down of the word line boosting signal PX is slower than the row address signal AX23, the PMOS transistor P1 is turned off while the word line boosting signal PX is not discharged to logically low.